Field of the Invention
The invention relates to a high density integrated semiconductor memory with an n-channel-EPROM cell in the form of a pillar. An n.sup.+ -doped source region runs along the base of the pillar and an n.sup.+ -doped drain-region is arranged on the pillar. The pillar also has an n.sup.+ -doped floating gate and a control gate. The lateral measurements of the pillar are chosen such that the pillar in a potential free state of the n-channel-EPROM cell is fully depleted of free charge carriers. The floating gate is disposed on the side walls of the pillar and encloses the pillar. The control-gate encloses the pillar and the floating-gate and it is disposed on the side walls of the pillar with an intermediate insulator layer at least in one subregion. The invention furthermore relates to a method for producing such a semiconductor memory.
In high density integrated semiconductor memories, particularly in electrically programmable, non-volatile memories (EPROMs), the integration density is limited, inter alia, by the structural resolution of photolithography. Minimum cell areas of about 7*F.sup.2 have already been produced by means of lateral integration of stacked gate flash cells in a NAND arrangement. F in this case indicates the minimum length which can be achieved by photolithography--referred to as the minimum feature size.
Greater integration density can be achieved with a vertical design of the EPROM cells, which are transistors in the form of cylinders or pillars. Stacked gate flash cells with a cell area of about 4.4*F.sup.2 can be produced using 1 .mu.m cylinders. Smaller cell areas cannot be produced using this technique, since the cylinders are already at the limit of structural fineness of the photographic technique. In addition, if the cylinder diameter is reduced further, these cylinders are fully depleted, so that the cell transistors no longer switch off in the discharged state. This effect is comparable to the overerase problem with stacked gate memories.
A highly integrated semiconductor memory of the above-mentioned type is known from U.S. Pat. No. 5,414,287 to Hong. That semiconductor memory is produced by a method in which on a p.sup.+ -doped substrate etching masks are produced, an anisotropic etching for the production of pillars is carried out, an n.sup.30 -implantation in the back-etched substrate regions is carried out, an oxide is grown on the pillars and the surfaces therebetween, n.sup.+ -doped polysilicon for the production of the floating gate is deposited and removed in the area of the surfaces located between the pillars. The removal is effected by anisotropic etching. An interpolydielectric is deposited on the n.sup.+ -doped polysilicon, an n-doped polysilicon layer is deposited for forming a control gate, the second polysilicon layer is etched isotropically, so that the second polysilicon layer still completely encloses the first polysilicon layer, the original etching mask is removed at the pillar tips, and the contacts are produced there.
A high density integrated semiconductor memory with a pillar structure is know from H. Pein and J. D. Plum, Performance of the 3-D Pencil Flasch EPROM Cell and Memory Array, U.S.-Z.: IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 42, No. Nov. 11, 1995, pages 1982-1991. There, the pillar is designed such that it is fully depleted of charge carriers.